FPG𝔸SIC

Последние публикации

• Automated SV Assertion Interface Generator: It generates a SV assertion interface for a given RTL design. It analyzes the RTL code to extract ports and registers, and creates an interface that can be used for writing as…

  27.05.2025 3 890 просмотров

• A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI Masala-CHAI is the first fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit…

  04.02.2025 5 160 просмотров

• Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA In terms of benchmarking memory, it can be done better on FPGA,…

  11.09.2024 5 820 просмотров

• FloorSet: The First Million-Scale Dataset for SoC Design Planning. FloorSet is aimed at advancing machine learning for floorplanning physical layouts of systems-on-a-chip (SoCs) and its sub-systems. It features 2 millio…

  15.08.2024 5 710 просмотров

• This element is a runtime, dynamically reconfigurable, LUT5 that enables the changing of the function of the LUT during circuit operation. Using the CDI pin, a new INIT to change the logical function.

  07.08.2024 4 690 просмотров

• Did you know that Xilinx FPGA have Dynamically Reconfigurable Look-Up Table (LUT)? It's called CFGLUT5 Note: This component occupies one of the eight LUT6 components within a CLBM. #UG974 #Xilinx #recongif

  07.08.2024 3 990 просмотров

• The new taste is unlocked: BiCMOS Now IHP providing not only 𝐨𝐩𝐞𝐧-𝐬𝐨𝐮𝐫𝐜𝐞 𝐏𝐃𝐊 but also 𝐟𝐫𝐞𝐞 𝐚𝐜𝐜𝐞𝐬𝐬 𝐭𝐨 𝐌𝐏𝐖 𝐫𝐮𝐧𝐬 to turn your designs into physical chips. This service is available exclusively for non-commercial projects.…

  08.07.2024 4 660 просмотров

• DUTCTL: A Flexible Open-Source Framework for Rapid Bring-Up, Characterization, and Remote Operation of Custom-Silicon RISC-V SoCs https://pulp-platform.org/docs/riscvmunich2024/RISCV_europe_summit_2024_DUTCTL_poster.pdf…

  27.06.2024 4 280 просмотров

• CompressedLUT - a tool for lossless compression of lookup tables and generation of their hardware files in Verilog and C++ for RTL and HLS designs. Links: 📄 https://doi.org/10.1145/3626202.3637575 💾 https://github.com/k…

  07.03.2024 5 520 просмотров

• Ramulator v2 - a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHamme…

  24.11.2023 6 030 просмотров